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Architecture of a Memory-Memory-Memory CLOS-Network Packet Switch for Large-Scale Switchs Using Internally-Buffered Switches and Scheduling Schemes to Transmit Packets in Sequence.
Case ID:
08-063
Web Published:
7/23/2018
Description:
https://www.google.com/patents/US8675673
Patent Information:
Title
App Type
Country
Serial No.
Patent No.
File Date
Issued Date
Expire Date
Patent Status
Direct Link:
http://njit.technologypublisher.com/technology/28238
Category(s):
Smart Information System
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For Information, Contact:
Simon Nynens
VP, Business Incubation
New Jersey Institute of Technology
simon.nynens@njit.edu
Inventors:
Roberto Rojas-Cessa
Ziqian Dong
Keywords:
Patent Issued
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