Asymmetric Error Correction & Flash‑Memory Rewriting Using Polar Codes

Technology Overview: This technology develops non‑linear polar‑code schemes for asymmetric channels and informed‑encoder settings typical of flash memory, enabling error correction combined with constrained rewriting that can avoid costly block erasures. The constructions achieve capacity on asymmetric channels with polynomial complexity, improving practical deployability for memory controllers.

Industry Pain Point: NAND flash has asymmetric program/erase physics; conventional ECC does not natively support rewrite without erase, causing endurance loss, latency, and energy overhead from frequent garbage collection and block erasures.

NJIT Solution: Use non‑linear polar codes and multicoding for informed‑encoder operation so new data can be written compatibly with current cell states, reducing erasures while maintaining robust error correction for storage reliability.

Key Features & Advantages

• Erase‑avoiding rewrite strategies mapped to flash constraints.
• Capacity‑achieving on asymmetric channels with polynomial storage/compute.
• Applicable to non‑volatile memory, optical channels, and broadcast scenarios.

Development Stage: TRL 2–3 – Algorithmic validation.

Target Markets

• SSD and controller vendors (client & enterprise)
• Embedded storage (IoT, automotive)
• Archival and high‑endurance NVM solutions